ASML and Chip Manufacturing

Why This Matters

Every advanced GPU used for AI training and inference (NVIDIA H100, B200, AMD MI300X) is manufactured using ASML's extreme ultraviolet (EUV) lithography machines. There is no alternative supplier. This makes ASML one of the most consequential single points of failure in the AI supply chain.

Understanding chip manufacturing is not optional for anyone thinking seriously about AI compute scaling. The question "can we train a 10x larger model next year?" depends on semiconductor fabrication capacity as much as it depends on algorithms. Scaling laws predict the compute needed, but the hardware supply chain determines whether that compute is available.

Mental Model

A chip is made by projecting patterns of light onto a silicon wafer coated with photosensitive material (photoresist). The smallest features you can print are limited by the wavelength of light. Shorter wavelength means smaller transistors. Smaller transistors mean more compute per chip.

EUV lithography uses 13.5nm wavelength light, roughly 14x shorter than the 193nm wavelength of the previous generation (deep ultraviolet, DUV). This is what enables sub-7nm transistor nodes.

The Physics of EUV

Definition

Rayleigh Resolution Criterion

The minimum resolvable feature size $W$ in optical lithography is:

$W = k_1 \cdot \frac{\lambda}{NA}$

where $\lambda$ is the wavelength, $NA$ is the numerical aperture of the projection optics, and $k_1$ is a process-dependent factor (typically $0.25 \leq k_1 \leq 0.5$).

For EUV: $\lambda = 13.5\text{nm}$, $NA \approx 0.33$ (current systems) or $0.55$ (High-NA, shipping 2025+). This gives minimum features around $8\text{nm}$ for current systems and potentially $5\text{nm}$ for High-NA.

Proposition

Lithography Resolution Scaling

Statement

At fixed $k_1$ and $NA$, the minimum feature size scales linearly with wavelength. The transition from DUV ($\lambda = 193\text{nm}$) to EUV ($\lambda = 13.5\text{nm}$) reduced the resolution limit by a factor of approximately 14, enabling the jump from multi-patterning at 7nm to single-patterning at comparable feature sizes.

Intuition

DUV lithography at 193nm hit a wall around 2015. To print features below about 40nm, fabs had to expose each layer multiple times with different masks (multi-patterning). This is slow, expensive, and introduces alignment errors. EUV eliminates the need for multi-patterning at current nodes, simplifying manufacturing and improving yield.

Failure Mode

The Rayleigh criterion is a first-order approximation. Real lithography involves stochastic effects (photon shot noise, resist chemistry randomness, subject to floating-point arithmetic limits in simulation) that become dominant at very small feature sizes. At sub-3nm nodes, even EUV will require multi-patterning or a transition to High-NA EUV.

How EUV Light Is Generated

EUV light cannot be generated by conventional lasers or lamps. The process:

1. A high-power CO2 laser fires at tin droplets (50,000 droplets per second, each about 25 micrometers in diameter).
2. Each droplet is hit twice: a pre-pulse flattens it into a pancake shape, then the main pulse vaporizes it into a plasma at approximately 500,000 degrees.
3. The tin plasma emits EUV radiation at 13.5nm.
4. Multilayer mirrors (alternating layers of molybdenum and silicon, each a few nanometers thick) collect and focus the EUV light. Each mirror reflects only about 70% of incident EUV, so a system with 10+ mirrors loses most of the light.
5. The collected EUV light projects a pattern from the reticle (mask) onto the wafer.

The conversion efficiency from laser power to usable EUV light is roughly 5-6%. A modern EUV system uses a 40kW CO2 laser to produce about 250W of EUV power at the wafer.

ASML's Position

ASML holds a monopoly on EUV lithography systems for several reasons:

Technology integration: An EUV scanner contains over 100,000 components from hundreds of suppliers. ASML is the integrator. Key subsystems come from Zeiss (optics), Trumpf (laser source), and ASML itself (stage and control systems). No other company has replicated this integration.

Development cost: ASML spent over 20 years and billions of euros developing EUV, with funding from Intel, Samsung, and TSMC. The technology was repeatedly declared impossible before it worked.

Installed base: Each EUV system costs roughly 200M to 400M USD (High-NA systems cost over 350M USD). TSMC, Samsung, and Intel are the primary customers. Total installed base is roughly 200+ systems worldwide as of early 2026.

Supply Chain Concentration

The semiconductor supply chain has multiple single points of failure:

Component	Dominant Supplier	Market Share
EUV lithography	ASML	~100%
EUV optics	Zeiss SMT	~100%
Advanced logic fabrication	TSMC	~90% at sub-5nm
HBM memory	SK Hynix, Samsung	~95% combined
Advanced packaging (CoWoS)	TSMC	~90%

A disruption at any of these points constrains AI chip supply. The geographic concentration (Netherlands, Germany, Taiwan, South Korea) adds geopolitical risk.

Relevance to AI Compute

The connection from lithography to AI models:

1. Transistor density determines compute per chip. The H100 has 80 billion transistors on TSMC 4nm (which uses EUV). The B200 has approximately 208 billion transistors on TSMC 4NP.
2. EUV throughput limits chip supply. Each EUV system processes roughly 100-150 wafers per hour. A single wafer yields a limited number of large AI chips (the H100 die is about 814mm^2).
3. High-NA EUV enables future scaling. The next generation of AI chips (2nm and below) will require High-NA EUV, of which ASML has delivered only a handful of systems to date.
4. Capital expenditure is enormous. A leading-edge fab costs $20B+ to build and equip. The EUV systems alone account for a significant fraction of this cost.

Common Confusions

Watch Out

Node names do not correspond to physical dimensions

TSMC 3nm does not mean transistors with 3nm features. Node names are marketing labels. Actual minimum metal pitch on TSMC N3 is approximately 23nm. The relationship between node names and physical dimensions diverged around 2010.

Watch Out

ASML does not fabricate chips

ASML makes the lithography machines. TSMC, Samsung, and Intel use those machines to fabricate chips. ASML is an equipment vendor, not a foundry. The distinction matters: ASML's bottleneck is machine production capacity, while TSMC's bottleneck is fab utilization and yield.

Watch Out

More EUV machines does not linearly increase chip output

Chip manufacturing involves 60-80 lithography steps, of which only a fraction use EUV (the rest use DUV). Other steps (deposition, etching, inspection, packaging) also constrain throughput. Adding EUV capacity helps only if it is the binding constraint.

Exercises

ExerciseCore

Problem

An EUV system with $\lambda = 13.5\text{nm}$ and $NA = 0.33$ uses $k_1 = 0.3$. What is the minimum resolvable feature size? How does this change with High-NA ($NA = 0.55$)?

Hint

Reveal Solution

ExerciseAdvanced

Problem

If each EUV mirror reflects 70% of incident light and the optical system has 11 mirrors, what fraction of the source EUV power reaches the wafer? If the source produces 250W, how much power is available for exposure?

Hint

Reveal Solution

References

Canonical:

• Mack, Fundamental Principles of Optical Lithography (2007), Chapters 1-3

Current:

• ASML Annual Reports and Technology Updates (2024-2025)
• Jiang & Wong, "EUV Lithography for Advanced Semiconductor Manufacturing" (Nature Reviews Electrical Engineering, 2024)